Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspective in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies and low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented

Development and characterizations of fine pitch flip-chip interconnection using silver sintering

International audienceFlip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Development and characterizations of fine pitch flip-chip interconnection using silver sintering

Flip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Design and fabrication of an ultra-thin silicon vapor chamber for compact electronic cooling

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Characterizations of indium interconnects for 3D quantum assemblies

International audienceLarge-scale integration of quantum bits and quantum technologies relies on multi-chip assemblies. In that context, we focus on indium microbumps to connect chips made from different materials and technological nodes. We have fabricated two test vehicles, comprising GaAs and Si chips stacked by die-to-die process on a Si-based multi-chip module. GaAs on Si and Si on Si daisy chains were compared to evaluate the impact of thermal expansion coefficient mismatch on the chip connection. Electrical measurements in a cryostat from 300 K to 2 K, as well as morphological and mechanical characterizations were used to support this study and qualify In interconnect technology for heterogeneous quantum assemblies

A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

International audienceThis paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip

3D Silicon Photonic Interposer Process Integration for Chiplet based 3D Systems

International audienceThis paper presents the process integration and technology development of a photonic interposer designed to host 4 chiplets (28 nm FDSOI) each integrating 16 cores and 6 RX/TX drivers (28 nm FDSOI) 3D stacked for many-core systems

Process Integration of Photonic interposer for Chiplet-based 3D Systems

International audienceThis paper presents the integration of a photonic interposer designed to host 4 chiplets (28nm FDSOI) each integrating 16 cores and 6 RX/TX routers (28nm FDSOI) 3D stacked for many-core systems.Exascale computer has been one of the main driver in the field of HPC and Datacom and has recently been reached mainly thanks to co-design approach. The next breakthrough in HPC integration will probably come through photonic technology and optical network-on-chip (ONoC) to overpass the bandwidth and the latency limitations of electrical links [1]. This paper will detail the integration and the fabrication on the 200mm Leti platform of a Si photonic interposer on SOI wafers featuring Si 310nm on 800nm thick buried oxide (BOX). The photonic circuit operating at 1310nm wavelength is composed of silicon passive structures (Rib waveguides, SPGC, …) and actives devices (SiGeSi photodiodes, PIN ring modulators). TiN heaters embedded in SiO2 above the ring modulators allow tuning wavelength resonance of the device. Active devices and heaters are connected to the BEOL using W contacts. The TSV middle process (12x100µm) is detailed with the implementation of SiN sacrificial layer above photonic FEOL to protect W plugs. The 4 metals layers back-end process with 2 layers optimized for RF signals is also introduced as well as micropillars (Fig 1 - right). The backside processing is then explained with the interposer thinning at 100µm and a thermal cavity etching above the heatersThe propagation losses are measured on RIB and DRIB structures and the insertion losses on SPGC structures both at the end of the FEOL and the BEOL process. The impact of the thermal back-end processes is then discussed.The TSV mid resistance have been evaluated with Kelvin test structure and daisy chains. The resistance is evaluated 95 % with the nominal diameter of 12µm. The dispersion of resistance values with the TSV diameter is also studied in the range of ± 1µm. The BEOL metal layers are characterized with DC test structures after each metal layer to evaluate the metal sheet resistance, the via resistance, the yield and the leakage current. The evolution of the metal and via performances within the processes is studied. Lock-in thermography analysis is performed on daisy chains and completed with Focused ion beam (FIB) cross-sections.The study has qualified all individual integration blocks required for the functional ONoC system developed currently in our group